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KB00381: Time reading latencies on SYNCCLOCK32 cards.

Reading time from the card for events that occur within our software. It takes approximately 200 nanoseconds to read each of the 32 bit zero latency low and high order time registers from the time your c code executes the

timelo=*(volatile unsigned long*)(BASE+Sec10_Usec1_Port);


timehi=*(volatile unsigned long*)(BASE+Year1_Min1_Port);

code. This assumes that there are no blocked PCI bus branches between the root of the PCI bus and the branch the XXX-SYNCCLOCK is on.  The MATCH output will occur within 200ns of the programmed time

Time stamping of a trigger in:

The time stamp is available 100 nsec after the external event input pulse. The PCI bus overhead for reading the 2 32bit (and 1 8bit for 100ns digit if you want) external time registers is 200 nsec per read.

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